A recent report from Taiwan has indicated that the Taiwan Semiconductor Manufacturing Company (TSMC) will begin mass producing its 2-nanometer semiconductor process in 2025, which aligns with TSMC’s previously stated timeline at analyst conferences. In addition, there are rumors that TSMC is planning to introduce a new 2-nanometer node called N2P, which is expected to go into production after N2.
TSMC has not yet confirmed the existence of N2P, although they have used similar naming conventions in the past for their 3-nanometer semiconductor technologies, such as N3P representing an improved version of N3 that reflects advances in the manufacturing process.
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According to sources in Taiwan’s supply chain, TSMC’s mass production of 2-nanometer semiconductors is progressing as planned. The company’s management has previously stated their timeline for this next-generation manufacturing process on several occasions, including during a conference in 2021 where TSMC’s CEO Dr. C.C.
Wei expressed confidence in achieving mass production of 2-nanometer semiconductors by 2025. Today’s report is based on information obtained from these sources.
Last year, TSMC’s Senior Vice President for Research and Development and Technology, Dr. Y.J. Mii, verified the previously mentioned timeline. More recently, in January, TSMC’s CEO Dr. Wei stated that the company is “ahead of schedule” and that the 2-nanometer semiconductor process will move to the test production phase in 2024, which is consistent with TSMC’s established timeline.
The new rumors expand on these remarks by suggesting that TSMC’s Baoshan facilities in Hsinchu will be used for mass production. This location is TSMC’s preferred site for implementing the advanced technology, and the company is also constructing a second facility in Taichung, Taiwan. The Taichung facility, known as Fab 20, will be built in stages and was announced by TSMC’s management in 2021 when they acquired the land for the plant.
The report also includes an intriguing piece of information about an alleged N2P process. Although TSMC has announced a high-performance version of the N3 process node called N3P, they have not yet provided similar details for the N2 process node.
According to sources in the supply chain, N2P may use back-side power delivery (BSPD) to enhance its performance. While the production of tiny transistors that are thousands of times smaller than a human hair is the most widely recognized aspect of semiconductor fabrication, there are other equally intricate areas that restrict manufacturers from improving chip performance.
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One area that presents a challenge is the wiring on a silicon component. Since the transistors must be linked to a power supply, the wires that connect them must also be extremely small due to the minuscule size of the transistors. An important restriction for new process technologies is the positioning of these wires. Typically, in the initial version of a process, the wires are situated above the transistors, while in subsequent generations, they are placed below them.
BSPD is the name given to the latter process, which is an extension of through-silicon vias (TSVs), a technique commonly used in the industry. TSVs are connections that traverse a wafer and enable multiple semiconductors to be stacked on top of each other, such as memory and processors.
A back-side power delivery network (BSPDN) involves bonding the wafers together and offers power efficiencies by delivering current to the chip via the backside, which has lower resistance and is more suitable for this purpose.
According to a research note by Morgan Stanley, TSMC has the option to revise its full-year 2023 revenue guidance from “slight growth” to flat, while its primary customer, Apple, may have to agree to a 3% increase in wafer prices later this year. The note also suggests that TSMC has enhanced its yields for the N3 process node, which is utilized in the iPhone.
Recent reports from Taiwan suggest that Taiwan Semiconductor Manufacturing Company (TSMC) is on track to start making its 2-nanometer chips by 2025. There are rumors about a new type of 2-nanometer chip called N2P, but TSMC hasn’t confirmed this yet. The company’s progress could affect its revenue and involve using advanced technologies like back-side power delivery.